IMPLEMENTING COMBINED FSM WITH CPLDS


IMPLEMENTING COMBINED FSM WITH CPLDS

Barkalov A.1, Titarenko L.1, Zeleneva I.2, Hrushko S.2

1Institute of Metrology, Electrotechnics and Informatics, University of Zielona Gora, Poland.
2Information Science and Computer Engineering Department, Zaporizhzhya National Technical University, Ukraine.
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ABSTRACT

The subject of the research in this article is the logic circuit of the combined finite state machine (CFSM), which combines the functions of the both FSM Mealy and Moore. In practice, such a model of control automata is used widely, but in the literature there is almost no theoretical description CFSM models and ways to optimize them. The article considers the problem of optimizing the logic of the combined finite state machine implemented in complex programmable logic devices (CPLD) basis. The CFSM circuit using programmable array logic (PAL) macrocells is implemented. The number of CPLD components, required to implement the logic of the automaton circuit, depends on the CFSM parameters and characteristics of element basis. Obviously, the reduction of necessary number of components leads to a decrease area occupied CFSM scheme in CPLD, thereby leads to reducing the hardware amount and power consumption in the circuit, and as result, increases the efficiency of the whole project. To solve the problem of CFSM optimization for a criterion of hardware expenses in this article it’s proposed to use the structural features of the basis CPLD, as well as the method of pseudoequivalent states. The FSM states are defined as a pseudoequivalent, if they mark some vertices linked with the input of the same next vertex in flow-chart. The proposed method includes the following steps: forming a plurality of CFSM states; encoding of states; forming a set of classes pseudoequivalent states; formation PALer blocks and tables; implementation of the CFSM scheme in a given element basis, such as CPLD. As a result, it’s possible to reduce the necessary number of PAL macro cells for implementing CFSM circuit in CPLD. The general result is a decreasing of in the total area of CFSM circuit on a chip. The advisability conditions of this method are discussed.

Keywords: combined FSM, CPLD, PAL, pseudoeguivalent states.
 
 
 
 
 

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